Ocaml Waveterm

eval $(opam env)
ocaml example.ml

#use "topfind";;
#require "hardcaml";;
#require "hardcaml_waveterm";;

open Base
open Hardcaml
open Hardcaml_waveterm

let create_counter () =
  let open Signal in
  let clk = input "clk" 1 in
  let clr = input "clr" 1 in
  let a = input "a" 16 in
  
  let reg_spec = Reg_spec.create () ~clock:clk ~clear:clr in
  
  let b = reg reg_spec ~enable:vdd (a +:. 1) in
  let lsb = reg reg_spec ~enable:vdd (sel_bottom a 1) in
  
  Circuit.create_exn 
    ~name:"counter"
    [ output "b" b
    ; output "lsb" lsb
    ]
;;

let testbench () =
  let circuit = create_counter () in
  let sim = Cyclesim.create circuit in
  let waves, sim = Waveform.create sim in
  
  let clk = Cyclesim.in_port sim "clk" in
  let clr = Cyclesim.in_port sim "clr" in
  let a = Cyclesim.in_port sim "a" in
  
  (* Reset sequence *)
  clr := Bits.vdd;
  clk := Bits.gnd;
  Cyclesim.cycle sim;
  
  clr := Bits.gnd;
  
  (* Test pattern - several cycles with different values *)
  a := Bits.of_int ~width:16 23;
  clk := Bits.vdd;
  Cyclesim.cycle sim;
  clk := Bits.gnd;
  Cyclesim.cycle sim;
  
  a := Bits.of_int ~width:16 45;
  clk := Bits.vdd;
  Cyclesim.cycle sim;
  clk := Bits.gnd;
  Cyclesim.cycle sim;
  
  a := Bits.of_int ~width:16 100;
  clk := Bits.vdd;
  Cyclesim.cycle sim;
  clk := Bits.gnd;
  Cyclesim.cycle sim;
  
  clk := Bits.vdd;
  Cyclesim.cycle sim;
  clk := Bits.gnd;
  Cyclesim.cycle sim;
  
  waves
;;

let () =
  let waves = testbench () in
  Waveform.print ~display_height:25 ~display_width:100 ~wave_width:2 waves;
;;

┌Signals───────────┐┌Waves─────────────────────────────────────────────────────────────────────────┐
│clk               ││┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  │
│                  ││   └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──│
│clr               ││──────┐                                                                       │
│                  ││      └───────────────────────────────────────────────                        │
│                  ││──────┬───────────┬───────────┬───────────────────────                        │
│a                 ││ 0000 │0017       │002D       │0064                                           │
│                  ││──────┴───────────┴───────────┴───────────────────────                        │
│                  ││────────────┬───────────┬───────────┬─────────────────                        │
│b                 ││ 0000       │0018       │002E       │0065                                     │
│                  ││────────────┴───────────┴───────────┴─────────────────                        │
│lsb               ││            ┌───────────────────────┐                                         │
│                  ││────────────┘                       └─────────────────                        │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
│                  ││                                                                              │
└──────────────────┘└──────────────────────────────────────────────────────────────────────────────┘