NajaEDA is a Python library for working with digital netlists. It provides a clean API for loading, analyzing, and modifying Verilog designs programmatically.

Hello World Link to heading

The first example parses a simple Verilog module and prints instances and nets.

module and_gate (input a, b, output y);
    
    and u1 (y, a, b);
endmodule

module adder (input a, input b, output y);

    and_gate u_and (
        .a(a),
        .b(b),
        .y(y)
    );
endmodule

from najaeda import netlist

top = netlist.load_verilog("adder_simple.v")

print("Top module:", top.get_name())

print("\nInstances:")
for inst in top.get_child_instances():
    print(" -", inst.get_name(), ":", inst.get_model_name())

print("\nNets:")
for net in top.get_nets():
    print(" -", net.get_name())

The output is as follows:

Top module: adder

Instances:
 - u_and : and_gate

Nets:
 - 
 - 
 - a
 - b
 - y

Connections:
 u_and.a -> a
 u_and.b -> b
 u_and.y -> y

Modifying the Netlist Link to heading

The really cool feature is that we can make changes to the parsed netlist and dump a new one. In this example, we rename an instance name and a net name. This is useful for ECO (Engineering Change Order) workflows.

inst = list(top.get_child_instances())[0]
inst.set_name("u_and_gate_renamed")

net = top.get_net("a")
if net:
    net.set_name("wire_renamed")

print("\nAfter modifications:")
for inst in top.get_child_instances():
    print(" -", inst.get_name(), ":", inst.get_model_name())

top.dump_verilog("adder_modified.v")

module and_gate(input a, input b, output y);
and u1(y, a, b);
endmodule //and_gate

module adder(input a, input b, output y);
wire wire_renamed;

assign wire_renamed = a;

and_gate u_and_gate_renamed (
  .a(wire_renamed),
  .b(b),
  .y(y)
);
endmodule //adder