OpenSTA is part openROAD project for RTL-GDS open source flow
OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.
Installation Link to heading
CUDD Link to heading
OpenSTA needs CUDD to deal with BDDs under the hood.
The CUDD package is a package written in C for the manipulation of decision diagrams. It supports binary decision diagrams (BDDs), algebraic decision diagrams (ADDs), and Zero-Suppressed BDDs (ZDDs).
wget https://raw.githubusercontent.com/davidkebo/cudd/main/cudd_versions/cudd-3.0.0.tar.gz
tar xvf cudd-3.0.0.tar.gz
cd cudd-3.0.0
./configure --prefix=$HOME/.local
make
make install
OpenSTA Link to heading
Now we have CUDD compiled and installed. We can compile OpenSTA linking to CUDD.
mkdir build
cd build
cmake -DCUDD_DIR=../cudd-3.0.0 -DCUDD_LIB=$HOME/.local/lib/libcudd.a ..
make
Hello worlds Link to heading
First we need to get the liberty file with reasonable information for timing estimation
wget https://github.com/The-OpenROAD-Project/alpha-release/blob/master/flow/platforms/nangate45/NangateOpenCellLibrary_typical.lib
Now, we can run yosys then sta scripts
yosys synth.ys
sta sta.tcl
Yosys Link to heading
For the first example, we can use small example of an inverter. Let’s name it example.v
module top(a, out);
input a;
output out;
assign out = ~a;
endmodule
Next step is small yosys script called synth.ys. It generates synth.v
read_verilog example.v
synth -top top
abc -liberty NangateOpenCellLibrary_typical.lib
clean
write_verilog synth.v
stat
The stat command will print the following statistics.
5. Printing statistics.
=== top ===
Number of wires: 2
Number of wire bits: 2
Number of public wires: 2
Number of public wire bits: 2
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1
INV_X1 1
STA Link to heading
Now we have netlist, We can create simple sdc example.sdc to feed to openSTA.
create_clock -name CLK -period 1000
set_input_delay 5 -clock CLK [get_ports a]
set_output_delay 5 -clock CLK [get_ports out]
Then run sta.tcl using the liberty file and calling report_checks
read_verilog synth.v
read_liberty NangateOpenCellLibrary_typical.lib
link_design top
read_sdc example.sdc
report_checks
report_tns
report_wns
exit
OpenSTA dumps the following report with Slack value after calculating the arrival time and required time.
Startpoint: a (input port clocked by CLK)
Endpoint: out (output port clocked by CLK)
Path Group: CLK
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock CLK (rise edge)
0.00 0.00 clock network delay (ideal)
5.00 5.00 v input external delay
0.00 5.00 v a (in)
0.29 5.29 ^ _0_/ZN (INV_X1)
0.00 5.29 ^ out (out)
5.29 data arrival time
1000.00 1000.00 clock CLK (rise edge)
0.00 1000.00 clock network delay (ideal)
0.00 1000.00 clock reconvergence pessimism
-5.00 995.00 output external delay
995.00 data required time
---------------------------------------------------------
995.00 data required time
-5.29 data arrival time
---------------------------------------------------------
989.71 slack (MET)