class A;
	uvm_blocking_put_port #(obj) m_port;

	task run_phase()
		m_port.put(pkt);
	endtask

endclass


class B;
	uvm_blocking_put_export #(obj, comp) m_imp;

	virtual task put(pkt p);
	endtask

endclass

a.m_port.connect(b.m_imp);

class A;
	uvm_blocking_get_imp #(obj) m_imp;

	virtual task get(pkt p);
	endtask

endclass

class B;
	uvm_blocking_get_port #(obj, comp) m_port;

	task run_phase()
		m_port.get(pkt);
	endtask

endclass

b.m_port.connect(a.m_imp);

m_subcompo.m_port.connect(this.m_port)

m_export.connect(subcomp.m_imp)

subcom.m_port.connect(comp.m_export)

uvm_blocking_put_port #(pkt) m_put;
m_put(p);


uvm_blocking_get_port #(pkt) m_get;
m_get(p)

uvm_tlm_fifo #(pkt) m_tlm_fifo;

comp1.m_put.connect(m_tlm_fifo.put_export);
comp2.m_get.connect(m_tlm_fifo.get_export);

uvm_analysis_port #(pkt) ap;
ap.write(p)

in uvm_subscriber
  uvm_analysis_imp #(T, this_type) analysis_export;


class s extends uvm_subscriber #(pkt);
	virtual function void write(pkt p1);
	endfunction

endclass

c1.ap.connect(c2.analysis_export)

// declare fifo
 uvm_tlm_analysis_fifo #(transaction) analy_fifo;  

// on one side create ap
 uvm_analysis_port#(transaction) analysis_port; 

// connect fifo to ap
 analysis_port.connect(analy_fifo.analysis_export);

// write to port
analysis_port.write(trans);

// get from fifo
analy_fifo.get(trans);

`uvm_put_imp_decl(_1)
`uvm_put_imp_decl(_2)

uvm_put_imp_2 #(pkt, my_put_compo#(pkt) ) put_imp2
uvm_put_imp_1 #(pkt, my_put_compo#(pkt) ) put_imp1

function void put_1(input pkt t);
endfunction
function void put_2(input pkt t);
endfunction


uvm_blocking_put_port #(pkt) put_port;
put_port.put(p);

compoS1.put_port.connect(compoR.put_imp1);
compoS2.put_port.connect(compoR.put_imp2);