task body();

	pkt t = pkt::type_id::create("t");

	start_item(t);

	tx.randomize();

	finish_item(t);
	get_response(r);
endtask

class mydriver extends uvm_driver #(pkt);

	seq_item_port.get_next_item(pkt);

	seq_item_port.item_done();
endclass


or for response

```verilog
class mydriver extends uvm_driver;
	seq_item_port.get(req);

	// create rsp
	rsp.set_id_info(req);
	seq_item_port.put(rsp);
endclass

m_drv.seq_item_port.connect(m_seqr.seq_item_export)