This post is about the Makefile shipped with cocotb. I will trace Makefiles targets for iverilog but most of the target are generic.
Startin with final outupt with “make -n” when running one of the examples examples/adder/tests/
cd cocotb/examples/adder/tests
export PYTHONPATH=$PWD/../model:$PYTHONPATH
echo "+timescale+1ns/1ps" > sim_build/cmds.f
iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s adder -f sim_build/cmds.f -g2012 ../hdl/adder.sv
MODULE=test_adder TESTCASE= TOPLEVEL=adder TOPLEVEL_LANG=verilog vvp -M ../../../.venv/lib/python3.8/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
So, How do we get here? Starting with examples/adder/tests/Makefile, where Makefile.sim is included.
include $(shell cocotb-config --makefiles)/Makefile.sim
And in Makefile.sim
include $(COCOTB_MAKEFILES_DIR)/simulators/Makefile.$(SIM_LOWERCASE)
And in Makefile.icarus
65 COMPILE_ARGS += -f $(SIM_BUILD)/cmds.f -g2012 # Default to latest SystemVerilog standard
66
67 # Compilation phase
68 $(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
69 @echo "+timescale+$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)" > $(SIM_BUILD)/cmds.f
70 $(CMD) -o $(SIM_BUILD)/sim.vvp -D COCOTB_SIM=1 $(TOPMODULE_ARG) $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
71
72 # Execution phase
73
74 $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
75 $(RM) $(COCOTB_RESULTS_FILE)
76
77 MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
78 $(SIM_CMD_PREFIX) $(ICARUS_BIN_DIR)/vvp -M $(shell cocotb-config --lib-dir) -m $(shell cocotb-config --lib-name vpi icarus) $(SIM_ARGS) $(EXTRA_ARGS) $(SIM_ BUILD)/sim.vvp $(PLUSARGS)
79
80 $(call check_for_results_file)
Also, in Makefile.inc is included where all common targets and env vars are defined.
include $(shell cocotb-config --makefiles)/Makefile.inc