I came across this riscv core. I was more interested in the setup to run Yosys and nextpnr all the way to bitstream.

The default target is board with ICE40 FPGA. These are steps the Makefile used to build bitstream.

Pre-synthesis Link to heading

starting with icepll, it’s part of icestorm project to reverse-engineer the binary format for ICE40 fpga.

icepll -q -i 12 -o 48 -m -f pll.sv

The generated pll is wrapper around Lattice’s SB_PLL40_CORE. I guess pll was needed to generated higher frequency. the on-baoard clock was 12 MHz and generated clock is 48 MHz.

module pll(
	input  clock_in,
	output clock_out,
	output locked
	);

SB_PLL40_CORE #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),		// DIVR =  0
		.DIVF(7'b0111111),	// DIVF = 63
		.DIVQ(3'b100),		// DIVQ =  4
		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.REFERENCECLK(clock_in),
		.PLLOUTCORE(clock_out)
		);

endmodule

Synthesis Link to heading

Yosys is OSS verilog synthesis tool. It support ICE40 and ECP5 lattice FPGAs.

yosys -q ice40.ys

ice40.ys reads top.sv, elaborate the the design, then finally synth for ice40 and generate both json and blif.

read_verilog -DICE40 -noautowire -sv top.sv
proc
opt -full
alumacc
share -aggressive
opt -full
synth_ice40 -abc2 -top top -blif top.blif -json top.json

Place and route Link to heading

Nextpnr is OSS FPGA PNR tool by the same people who did Yosys.

nextpnr takes synthesis json, pcf and configuration.It generate .asc file for icepack.

nextpnr-ice40 -q --hx8k --package ct256 --json top.json --pcf boards/ice40hx8k-b-evn.pcf --freq 48 --asc top_syn.asc

.asc is ASCII file to represent tile. utilities from icestorm project can pack and unpack asc files into and from bitstream.

Bitstream generation Link to heading

icepack is part of of icestorm project which converts .asc to bitstream.

cp top_syn.asc top.asc
icepack -s top.asc top.bin